WebFPGA Synthesis Made Simple

Kickoff

25 Feb 2019, Ryan Jacobs

kick·off noun
the start of something : commencement

I’m just getting the infrastructure up right now, which explains this initial blog post. Testing out syntax highlighting and all that jazz…

Some sample Verilog code to get your feet wet:

// blinky.v
//
// Internal HFOSC runs ~48Mhz. Use counter to count to 1 second.
//
// 1/48,000,000 == 20.833ns == period. Counting to 48 million will yield 1 second.
// Spec is to toggle twice a second: on for 0.5s, then off for 0.5s.
// So we need to count to 24 million, hence a 25 bit counter.
//
// @MAP_IO LED 31
// @CAS_CLK pin OSC_i/CLKHF 20.833 // 20.833ns is 48 MHz

module fpga_top(output reg LED);
  // setup clock
  wire clk_en;
  assign clk_en = 1'b1;
  reg [24:0] counter;

  // clock macro
  SB_HFOSC OSC_i (
    .CLKHFEN(clk_en),
    .CLKHFPU(clk_en),
    .CLKHF(clk)
  );
 
  // blink the LED twice a second
  always @ (posedge clk)
    if (counter == 24000000)
      begin
        LED      <= ~LED;
        counter  <= 'b0;
      end
  else
    begin
      counter <= counter + 'b1;
  end
endmodule